Intel BCLK Governor - SkatterBencher

BCLK governor is an integrated circuit that calculates the BCLK frequency and prevents the CPU from running the BCLK above the allowed limit. Importantly, BCLK calculation doesn’t rely on using the Integrated Clock Controller (ICC) from the PCH as it works with external clocks as well. The BCLK Governor has been present on Intel CPUs since Skylake.

Pre-BCLK Governor Restricted BCLK overclocking

With the Introduction of Nehalem and the Core i7 processors in November 2008, Intel introduced two important technologies: Turbo Mode and the Power Control Unit. The Power Control Unit is a one million-plus transistor on-die microcontroller managing the CPU cores. It has its firmware and uses inputs like temperature, current, power, and OS requests to manage the CPU core frequency and power. Long story short: the PCU controls the CPU behavior.

With the integration of the Power Control Unit, Intel has a much tighter grip on everything related to overclocking. While Nehalem still relied on an external clock generator provided by the motherboard, Intel integrated the clock generator for Sandy Bridge in the PCH.

As it would turn out, the BCLK overclocking capabilities of Sandy Bridge processors were extremely limited as it was tied to the DMI and PCIe clocks. The best BCLK overclock is still only 111.86 MHz, not even 12% higher than the base frequency of 100 MHz. From Sandy Bridge onwards, Intel imposed restricted overclocking for non-K processors. For Sandy Bridge, Ivy Bridge, and Haswell, the maximum base clock frequency for non-K locked processors is limited to around 111 MHz.

Skylake BCLK Governor Issue

On December 2^nd, 2015, almost four months after the launch of Intel’s 6^th generation processors and brand-new CPU architecture, Skylake, the overclocking world woke up to a Core i3-6320 processor with an overclocked BCLK frequency of 120 MHz on a Supermicro H170 motherboard.

Supermicro had found a way to work around the Power Control Unit which is responsible for managing the CPU’s power consumption, performance, as well as housing the BCLK Governor. With the PCU out of the way, there was no way to check the BCLK frequency and throw an error. So, non-K overclocking was back.

Unfortunately, disabling the PCU came with a couple of significant drawbacks. For example:

C-states are disabled; therefore, the CPU will constantly run at its highest frequency and voltage
Turbo-boost is disabled
Integrated graphics are disabled
AVX2 instruction performance is poor, approximately 4-5 times slower due to the upper 128-bit half of the execution units and data buses not being taken out of their power-saving states
CPU core temperature readings are incorrect

Despite the drawbacks, some motherboard vendors went all-in on promoting non-K overclocking. Most notably, ASRock set up an entire marketing campaign for its SKY OC feature. As expected, Intel pressured motherboard partners to remove non-K overclocking support, and most motherboard partners withdrew official support . That said, extreme overclockers and enthusiasts could still find and use the old BIOSes with non-K OC support.

The BCLK Governor measures the real-time BCLK frequency and checks it against a hard-coded limitation. Since Skylake, the BCLK limit is 103 MHz.

Alder Lake BCLK Governor Issue

The BCLK governor is a standard feature of the CPU microcode and monitors both the internal and external clock generator. Due to an apparent oversight, on Alder Lake processors, the BCLK governor does not function correctly on a specific older pre-release version of the CPU microcode 0x9.

The BCLK governor works correctly for the integrated clock generator but not for the external clock generator. Using this CPU microcode in combination with an external clock generator means you can increase the base clock frequency on a locked non-overclockable part beyond the artificial limitation of 103 MHz.

We can only speculate what caused this oversight. One theory is that this happened due to a fundamental change in the clocking structure. Since integrating the clock generator on Sandy Bridge, it’s always been the PCH that generates the 100MHz BCLK frequency. That was the case until Rocket Lake. However, first on Tiger Lake and now also on Alder Lake, BCLK is added on the CPU die. The 38.4 MHz crystal still connects to the PCH, but instead of driving a 100MHz clock to the CPU, it now just forwards that 38.4 MHz clock to the CPU BCLK PLL. The CPU, in turn, generates its 100MHz reference clock. This fundamental change in clocking structure may explain why the oversight occurred.

Later microcode versions don’t have this oversight, and non-K BCLK overclocking is restricted.