Intel Extreme Memory Profile 2.0 is the XMP standard for DDR4 memory and is the successor to XMP 1.3 for DDR3 memory. It was introduced together with introduction of DDR4 memory alongside the Haswell-E processors in 2014.
While original DDR4 JEDEC specification allowed for memory speeds up to DDR4-2133, at the Haswell-E platform launch XMP partners had Quad Channel kits available up to DDR4-3200. Today, XMP 2.0 kits up to DDR5-5333 are available. You can find the latest XMP kit database entries on Intel’s official website: https://www.intel.com/content/www/us/en/gaming/xmp-for-core-processors.html.
DDR4 DIMMs currently have at least a 512-byte SPD flash device which stores all of the memory device parameters and configuration details for that specific DIMM. SPD programming, as defined by the standard DDR4 JEDEC specifications.
Extreme Memory Profile 2.0 Technical Specification
DDR4 DIMMs have at least a 512-byte SPD flash device which stores all of the memory device parameters and configuration details for that specific DIMM. SPD programming, as defined by the standard DDR4 JEDEC specifications.
Block | Range | Description |
0 | 0~127 (0x000~0x07F) | Base Configuration and DRAM Parameters |
1 | 128~255 (0x080~0x0FF) | Module Specific Parameters |
2 | 256~319 (0x100~0x13F) 320~383 (0x140~0x17F) | Reserved Manufacturing Information |
3 | 384~511 (0x180~0x1FF) | End User Programmable |
XMP DDR4 DIMMs use bytes 384–511 to program specific profile details as defined in the Intel Extreme Memory Profile 2.0 Specification.
- Global Bytes 384 to 392: Global Parameters for Intel Extreme Memory used across all profiles.
- Byte 384 and 385: Intel XMP Identification String
- Bytes 393 – 439: Profile 1 programming
- Bytes 440 – 511: Profile 2 programming
The Global Section has only a few configurable fields:
- The XMP ID string
- The XMP version (this will be 2.0 for DDR5)
- The XMP organization (this allows memory vendors to enable or disable Profiles 1 and 2)
Each profile has a wide range of configurable fields related to voltage, frequency, and memory timings, including:
- Module VDD
- tCL
- tRCD
- tRP
- tRAS
- tRC
- tWR
- tRFC1
- tRFC2
- tRFC4
- tFAW
- tRRD_S
- tRRD_L
- tRC
- tAA