AMD UCLK DIV1 Mode enables forcing the memory controller to run at the same or half the system memory frequency.

uclk div1 mode

AMD Ryzen Memory Subsystem Interface

The memory subsystem of an AMD Ryzen CPU consists of the infinity fabric, the memory controller, and the system memory. The operating frequency of these three parts is driven by the SOC PLL. Each of these parts have their own PLL frequency:

  • FCLK = Fabric Clock Frequency
  • MCLK = Memory Clock Frequency
  • UCLK = Unified Memory Controller Clock Frequency
amd ryzen memory topology

Since the 1st generation Ryzen processor, the tuning capabilities of the memory subsystem changed quite a bit.

On the 1st generation Ryzen processors, UCLK runs by default at the same frequency as the system memory and the fabric frequency. So MCLK=UCLK=FCLK. Or put differently, it’s running the 1:1:1 ratio. However, from the 3rd generation Ryzen processors, users could run the fabric, memory controller, and memory frequency in asynchronous mode.

uclk fclk mclk


In asynchronous mode, the fabric, memory, and memory controller can run at independent frequencies.

The fabric clock can be clocked entirely independent from the two other parts. You can adjust the fabric clock in steps of 33 to 50 MHz depending on the range.

The memory controller can either run at the same or half the frequency of the system memory. The user can force either by configuring the UCLK DIV1 Mode option.

Thus, the maximum frequency is limited to the maximum supported memory ratio by the Ryzen processor. On Raphael processors, that’s up to 6000 MHz with the DDR5-12000 memory ratio.